Towards 40 Years of ASAP: From Systolic Arrays to Application-Specific Processing
By Wayne Luk, Professor, Imperial College London
Abstract:
The International Workshop on Systolic Arrays took place at the University of Oxford in July, 1986. It has since been held annually, becoming the International Conference on Application-Specific Systems, Architectures and Processors (ASAP) from 1996. This talk describes advances in systolic arrays and in application-specific processing, which have shown to have enduring importance for computer engineering. Many researchers and professionals have found that systolic arrays and application-specific processing are key to the development of accelerators for speeding up many applications involving artificial intelligence, enabling adoption of AI for the benefit of specific application domains. To illustrate accelerator development targeting AI for science, I will describe our collaboration with high-energy physics researchers at CERN in developing low-latency deep learning accelerator architectures. In particular, I will present a Graph Neural Network accelerator capable of achieving sub-microsecond latency to support online event selection in the Level-1 triggers at the CERN Large Hadron Collider experiments. Our efforts to automate the development of such accelerators based on meta-programming techniques will also be covered.
Bio:
Wayne Luk is Professor of Computer Engineering at Imperial College London, and the head of the Custom Computing Research Group in Imperial’s Department of Computing. He was a Visiting Professor at Stanford University. His research focuses on foundation and applications of hardware acceleration, reconfigurable systems, and design automation, and he has published over 600 papers in these areas. He was among the first to develop parametric neural network descriptions for hardware acceleration. His work has led to a Research Excellence Award from Imperial College London, and to over 15 awards from international conferences such as the International Conference on Application-specific Systems, Architectures and Processors (ASAP), the International Symposium on Field-Programmable Custom Computing Machines (FCCM), and the International Conference on Field-Programmable Logic and Applications (FPL). He co-founded BlueBee Technologies which was acquired by Illumina. He co-founded ACM Transactions on Reconfigurable Technology and Systems (TRETS) and was the first Editor-in-Chief. He is a Fellow of the Royal Academy of Engineering, a Fellow of the IEEE, and a Fellow of the BCS.
For ML and With ML: The New Normal in Hardware Design
By Lizy Kurian John, Professor, University of Texas at Austin
Abstract:
The emerging machine learning (ML) applications put exploding demands on hardware systems, and it is important to deliver high throughput, low latency and low energy consumption, in order to sustain the thriving development of cognitive systems and applications. Designing efficient circuits and systems to enable, support, and harness the power of machine intelligence is important to keep the present momentum of intelligent systems. In this talk, I will describe some of our research on providing efficient hardware infrastructure for ML.
In addition to designing systems for ML, we also conduct research on using ML in designing and evaluating systems. In this talk I’ll describe a few examples on using ML for pre-silicon performance evaluation during design of computer systems.
Bio:
Lizy Kurian John is Truchard Foundation Chair in Engineering at the University of Texas at Austin. She received her Ph. D in Computer Engineering from the Pennsylvania State University. Her research interests include workload characterization, performance evaluation, memory systems, reconfigurable architectures, and high performance architectures for emerging workloads. She is recipient of many awards including Joe J. King Professional Engineering Achievement Award (2023), The Pennsylvania State University Outstanding Engineering Alumnus Award (2011), the NSF CAREER award, UT Austin Engineering Foundation Faculty Award, Halliburton, Brown and Root Engineering Foundation Young Faculty Award, University of Texas Alumni Association (Texas Exes) Teaching Award, etc. She has coauthored books on Digital Systems Design using VHDL (Cengage Publishers, 2007, 2017), a book on Digital Systems Design using Verilog (Cengage Publishers, 2014) and has edited 4 books including a book on Computer Performance Evaluation and Benchmarking. She holds 18 US patents and is an IEEE Fellow, ACM Fellow, Fellow of AAAS, and Fellow of the National Academy of Inventors (NAI).