| Time | Session Type | Title / Description |
|---|---|---|
| Day 1 | ||
| 8:30 AM – 9:00 AM | Registration | |
| 9:00 AM – 12:00 PM | Workshop / Tutorial | Sponsor-organized Workshops and Tutorials |
| 12:00 PM – 1:30 PM | Luncheon | |
| 1:30 PM – 3:00 PM | Special Session | Special Session #1: ASAP since the Millennium — A Selection of Most Representative Papers (4 Invited Talks) |
| 3:00 PM – 3:30 PM | Coffee Break | |
| 3:30 PM – 5:00 PM | Special Session | Special Session #2: Custom Computing in Canada (4 Invited Talks) |
| 5:30 PM – 7:00 PM | Reception | |
| Day 2 | ||
| 8:30 AM – 8:45 AM | Registration | |
| 8:45 AM – 9:00 AM | Opening | Opening by General Chair and Program Chairs |
| 9:00 AM – 10:00 AM | Keynote | Keynote #1: Towards 40 Years of ASAP — From Systolic Arrays to Application-Specific Processing |
| 10:00 AM – 10:30 AM | Coffee Break | |
| 10:30 AM – 12:00 PM | Technical Session 1 |
Scalable Systems and Secure Acceleration (#3) AIRES: Accelerating Out-of-Core GCNs via Algorithm-System Co-Design (#42) Dynamic Allocation Scheme for Adaptive Shared-memory Mapping on Kilo-core RV Clusters for Attention-based Model Deployment (#45) Cryptonite: Scalable Accelerator Design for Cryptographic Primitives and Algorithms (#60) FAV-NSS: An HIL Framework for Accelerating Validation of Automotive Network Security Strategies Poster pitch: 1 min per poster |
| 12:00 PM – 2:00 PM | Luncheon + Poster | |
| 2:00 PM – 3:00 PM | Technical Session 2 |
Design Exploration and Emerging Hardware (#55) PRDSE: A Prior-Driven Design Space Exploration Method (#57) Trimming Down Large Spiking Vision Transformers via Heterogeneous Quantization Search (#72) X-pSRAM: A Photonic SRAM with Embedded XOR Logic for Ultra-Fast In-Memory Computing |
| 3:00 PM – 3:30 PM | Coffee Break | |
| 3:30 PM – 4:40 PM | Technical Session 3 |
RISC-V and Custom Architectures (#12) Labidus: RISC-V Overlay with Streaming Asynchronous Custom Instructions (#26) Ahead-of-Time Generation for GPSA Protection in RISC-V Embedded Cores (#64) SCAL: An Open-Source Scalable Core Adaptation Layer for Interfacing RISC-V ISA Extensions (#11) MXDOTP: A RISC-V ISA Extension for Enabling Microscaling (MX) Floating-Point Dot Products (short) |
| 5:30 PM – 9:00 PM | Campus Visit + Banquet | |
| Day 3 | ||
| 9:00 AM – 10:00 AM | Keynote | Keynote #2: For ML and With ML — The New Normal in Hardware Design |
| 10:00 AM – 10:30 AM | Coffee Break | |
| 10:30 AM – 11:50 AM | Technical Session 4 |
LLMs, Transformers, and Accelerators (#5) ReaLLM: Trace-Driven Framework for Rapid Simulation of Large-Scale LLM Inference (#49) METAL: Memory-Efficient Transformer Architecture for Long-Context Inference on FPGA (#56) MLA-LLM Hardware Acceleration with Tensor-Train Decomposition on Group Vector Systolic Accelerator (#73) SpiRec: Soft-logic Architecture Exploration of Reconfigurable Systems for Spiking Neural Networks |
| 11:50 AM – 1:30 PM | Luncheon | |
| 1:30 PM – 3:00 PM | Special Session | Special Session #3: Reconfigurable Edge Computing (4 Invited Talks) |
| 3:00 PM – 3:30 PM | Coffee Break | |
| 3:30 PM – 4:40 PM | Special Session | Special Session #4: Architectures for Sustainable Security (3 Invited Talks) |
| 4:40 PM – 5:00 PM | Closing | Awards + Closing Remarks |