Tentative Program Schedule

Time	Session Type	Title / Description
Day 1
8:30 AM – 9:00 AM	Registration
9:00 AM – 12:00 PM	Workshop / Tutorial	Sponsor-organized Workshops and Tutorials
12:00 PM – 1:30 PM	Luncheon
1:30 PM – 3:00 PM	Special Session 1	ASAP since the Millennium: A Selection of Most Representative Papers RETROSPECTIVE: [ASAP 2000] High-Level Synthesis of Nonprogrammable Hardware Accelerators Dr. Rob Schreiber (Cerebras Systems) RETROSPECTIVE: [ASAP 2003] Automatic Instruction Set Extension and Utilization for Embedded Processors Prof. Paolo Ienne (EPFL) RETROSPECTIVE: [ASAP 2005] Table-based Polynomials for Fast Hardware Function Evaluation Prof. Florent de Dinechin (INSA-Lyon) RETROSPECTIVE: [ASAP 2017] CGRA-ME: A unified framework for CGRA modelling and exploration Prof. Jason Anderson (University of Toronto)
3:00 PM – 3:30 PM	Coffee Break
3:30 PM – 5:00 PM	Special Session 2	Custom Computing in Canada Synthesizing Machine Learning Accelerators for FPGAs the Functional Way Prof. Christophe Dubach (McGill) Building Multi-FPGA Heterogeneous Computing Systems at Scale Prof. Paul Chow (University of Toronto) Machine Learning for FPGA Design Prof. Nachiket Kapre (University of Waterloo) Title TBD Prof. Steve Wilton (UBC)
5:30 PM – 7:00 PM	Reception
Day 2
8:30 AM – 8:45 AM	Registration
8:45 AM – 9:00 AM	Opening	Opening by General Chair and Program Chairs
9:00 AM – 10:00 AM	Keynote	Keynote #1: Towards 40 Years of ASAP: From Systolic Arrays to Application-Specific Processing (Keynotes)
10:00 AM – 10:30 AM	Coffee Break
10:30 AM – 12:00 PM	Technical Session 1	Scalable Systems and Secure Acceleration AIRES: Accelerating Out-of-Core GCNs via Algorithm-System Co-Design Shakya Jayakody, Youpeng Zhao, Jun Wang (University of Central Florida) A Dynamic Allocation Scheme for Adaptive Shared-memory Mapping on Kilo-core RV Clusters for Attention-based Model Deployment (Best Paper Candidate) Bowen Wang, Marco Bertuletti, Yichao Zhang, Victor J. B. Jung, Luca Benini (ETH Zurich) Cryptonite: Scalable Accelerator Design for Cryptographic Primitives and Algorithms Karthikeya Sharma Maheswaran, Camille Bossut, Andy Wanna, Qirun Zhang, Cong (Callie) Hao (Georgia Institute of Technology) FAV-NSS: An HIL Framework for Accelerating Validation of Automotive Network Security Strategies Changhong Li, Shashwat Khandelwal, Shreejith Shanker (Trinity College Dublin) Poster pitch: 1 min per poster
12:00 PM – 2:00 PM	Luncheon + Poster	Poster Presentations List
2:00 PM – 3:00 PM	Technical Session 2	Design Exploration and Emerging Hardware PRDSE: A Prior-Driven Design Space Exploration Method (Best Paper Candidate) Junda Zhu, Xiaoya Fan, Jianfeng An, Kaijie Feng (Northwestern Polytechnical University, School of Computer Science) Trimming Down Large Spiking Vision Transformers via Heterogeneous Quantization Search Boxun Xu, Yufei Song, Peng Li (University of California, Santa Barbara) X-pSRAM: A Photonic SRAM with Embedded XOR Logic for Ultra-Fast In-Memory Computing Md Abdullah-Al Kaiser (University of Wisconsin-Madison); Sugeet Sunder, Ajey P. Jacob (USC Information Sciences Institute); Akhilesh R. Jaiswal (University of Wisconsin-Madison)
3:00 PM – 3:30 PM	Coffee Break
3:30 PM – 4:40 PM	Technical Session 3	RISC-V and Custom Architectures Labidus: RISC-V Overlay with Streaming Asynchronous Custom Instructions Gongjin Sun (Samsung Semiconductor, Inc.); Seongyoung Kang, Jane He, Se-Min Lim, Sang-Woo Jun (University of California, Irvine) Ahead of Time Generation for GPSA Protection in RISC-V Embedded Cores Louis Savary (Inria); Simon Rokicki (ENS Rennes); Steven Derrien (LabSTICC) SCAL: An Open-Source Scalable Core Adaptation Layer for Interfacing RISC-V ISA Extensions Brindusa Mihaela Damian-Kosterhon (TU Darmstadt); Florian Meisel (Technical University of Darmstadt); Andreas Koch (Technische Universität Darmstadt) MXDOTP: A RISC-V ISA Extension for Enabling Microscaling (MX) Floating-Point Dot Products (short) Gamze Islamoglu, Luca Bertaccini (ETH Zürich); Arpan Suravi Prasad (ETH Zurich); Francesco Conti, Angelo Garofalo (University of Bologna); Luca Benini (ETH Zürich)
5:45 PM – 9:00 PM	Burnaby Campus Visit + Banquet
Day 3
9:00 AM – 10:00 AM	Keynote	Keynote #2: For ML and With ML: The New Normal in Hardware Design (Keynotes)
10:00 AM – 10:30 AM	Coffee Break
10:30 AM – 11:50 AM	Technical Session 4	LLMs, Transformers, and Accelerators ReaLLM: A Trace-Driven Framework for Rapid Simulation of Large-Scale LLM Inference Huwan Peng, Scott Davidson, C.-J. Richard Shi (University of Washington); Michael Taylor (U. Washington) METAL: A Memory-Efficient Transformer Architecture for Long-Context Inference on FPGA (Best Paper Candidate) Zicheng He (University of California, Los Angeles, USA); Shaoqiang Lu (Ningbo Institute of Digital Twin, Eastern Institute of Technology, Ningbo, China); Tiandong Zhao (University of California, Los Angeles, USA); Chen Wu (Ningbo Institute of Digital Twin, Eastern Institute of Technology, Ningbo, China); Lei He (University of California, Los Angeles, USA) An MLA-LLM Hardware Acceleration with Tensor-Train Decomposition on Group Vector Systolic Accelerator Sixiao Huang, Tintin Wang, Keyao Jiang, Ao Shen, Kai Li, Ang Li, Mingqiang Huang, HaoYu (Southern University of Science and Technology) SpiRec: Soft-logic Architecture Exploration of Reconfigurable Systems for Spiking Neural Networks Xunqin Lai, Federico Corradi (Eindhoven University of Technology); Siva Satyendra Sahoo (IMEC)
11:50 AM – 1:30 PM	Luncheon
1:30 PM – 3:00 PM	Special Session 3	Reconfigurable Edge Computing Managing Computation Offloading from Edge Devices to a Reconfigurable Edge Cloud Prof. Russell Tessier (University of Massachusetts, Amherst) Bio-Inspired Event Cameras for Robust Edge Hardware in Challenging Environments Prof. Christophe Bobda (University of Florida) ELLIE: Energy-Efficient LLM Inference at the Edge via Prefill–Decode Splitting Samuel Wiggins (University of Southern California) Reconfigurable Acceleration at the Edge: Blending FPGA Flexibility with CGRA Efficiency Dr. Mirjana Stojilović (EPFL)
3:00 PM – 3:30 PM	Coffee Break
3:30 PM – 4:40 PM	Special Session 4	Architectures for Sustainable Security Differential Power Analysis on Low-Energy Keystream Generating Hardware: Full-State Recovery in DIZY Implementation Prof. Elif Bilge Kavun (Barkhausen Institut and TU Dresden) Architectures for Sustainability in the Computing Continuum Prof. Francesco Regazzoni (University of Amsterdam, Netherlands, and Università della Svizzera italiana, Lugano, Swizterland) Unified FPGA Design of Kyber and Dilithium with Provable Fault Tolerance Prof. Debdeep Mukhopadhyay (IIT Kharagpur)
4:40 PM – 5:00 PM	Closing	Awards + Closing Remarks

Poster Presentations

PAMA: Large-Scale GNN Acceleration with Pre-Aggregation in Multi-Node Architecture
Weiwei Wu (Tsinghua University); Fengbin Tu (The Hong Kong University of Science and Technology); Shaojun Wei, Xiangyu Li, Yang Hu, Shouyi Yin (Tsinghua University)
High Performance Soft Multi-Processor Arrays
Martin Langhammer (Altera, Imperial College London); Kim Bozman, Gregg Baeckler (Altera)
FPGA-Based Acceleration for EMT Simulation of Electrical Distribution Network
Zhenrui Wang, Weiping Shi, Jiang Hu (Texas A&M University)
Noise Reduction on Hearing-Aid Processors: Traditional Methods vs. Neural Networks
Simon Christian Klein, Lando Rossol, Finn Venema, Sven Schönewald, Jens Karrenbauer, Holger Blume (Institute of Microelectronic Systems, Leibniz University Hanover)
An Application Mapping Algorithm for Mesh-based Hybrid Optical Network-on-Chip Architecture
Sucharita Samanta, Nandan Surani, Devarsh Patel, Vikas Dubey, Kanchan Manna (Birla Institute of Technology and Sciences Pilani, K K Birla Goa Campus)
Permuting Accumulation Order for Low-Precision Machine Learning
Ebby Samson, Tony Liu, Wayne Luk, George A. Constantinides (Imperial College London)
Exploration Framework for IDS Optimization on FPGA
Kévin Druart (Université of West Britanny, Brest, France); David Espes, Catherine Dezan (University of West Britanny, Brest, France); Alain Deturche (Thales DMS, Brest, France)
Scalable Malware Detection Framework Using Performance Counters and Gradient Boosting
Chutitep Woralert, Chen Liu, Zander Blasingame (Clarkson University)
High-Performance, Area-Efficient and Predictable Matrix Multiplication for ASIC
Alexander Lehnert, Liliia Almeeva (University of Rostock); Ralf Müller (Friedrich-Alexander-Universität Erlangen-Nürnberg); Marc Reichenbach (University of Rostock)
Integrated Security Mechanisms for Weight Protection in Memristive Crossbar Arrays
Muhammad Faheemur Rahman, Wayne Burleson (University of Massachusetts Amherst)
[SFU Special] SERI: High-Throughput Streaming Acceleration of Electron Repulsion Integral Computation in Quantum Chemistry using HBM-based FPGAs
Philip Stachura, Zhenman Fang (Simon Fraser University)
[SFU Special] AutoNTT: Automatic Architecture Design and Exploration for Number Theoretic Transform Acceleration on FPGAs
Dilshan Sampath, Zhenman Fang (Simon Fraser University)